• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    PURPOSE: A device and method for normalizing state values of a structure decoder in a mobile communication system are provided so that state values accumulated in a current state can be normalized and outputted, when exceeding a predetermined reference value. CONSTITUTION: At least two structure decoders are connected in a serial chain structure, for performing a decoding operation according to an iterative decoding method, in an iterative decoder of a mobile communication system. A device for normalizing state values of the structure decoder detects state values of the respective states transited from a current state to a succeeding state. When the respective state values exceed a predetermined reference value, the device subtracts a predetermined value from the state values. Accordingly, the state values are normalized, and transited to the succeeding state. Here, an addition comparison selecting unit serves to normalize the state values. As a result, the device for normalizing the state values of the structure decoder can remove an error due to an overflow, and efficiently utilize a memory, by normalizing the accumulated state values for decoding.
    公开号:KR20000046049A
    申请号:KR1019980062724
    申请日:1998-12-31
    公开日:2000-07-25
    发明作者:이영환；김민구；김병조；김세형
    申请人:윤종용；삼성전자 주식회사；
    IPC主号:
    专利说明:

    Apparatus and Method for Normalizing State Value of Component Decoder in Mobile Communication System
    The present invention relates to an iterative decoder and a decoding method using an iterative decoding method of a mobile communication system. It is about.
    In general, mobile communication systems such as the IMT-2000 system (CDMA2000) and the UMTS (NTT DoCoMo System) use an iterative decoding turbo code. Deep space communication systems and satellite communication systems that use code also use iterative decoding. This field is related to soft decision and optimal performance of error correcting code.
    FIG. 1 is a block diagram of a repeating decoder having two general configuration decoders. Hereinafter, the structure and operation of the repeater will be described with reference to FIG.
    The first component decoder 101 receives the corresponding redundancy Y1k through the demux 107 among the codeword Xk as the system metric information and the redundancy Yk as the parity information, and receives predetermined additional information. Decoding is performed to output a first decoded codeword (Xk) and extra information which is information about the decoded result. The interleaver 103 interleaves and outputs the first decoded codeword Xk. The second component decoder 105 decodes the primary decoded codeword Xk output from the interleaver 103, additional information output from the first component decoder 101, and the redundancy Yk. Through receiving the corresponding redundancy (Y2k) through the decode the codeword (Xk) and outputs the second decoded codeword (Xk) through the deinterleaver (111). In addition, the second component decoder 105 outputs additional information, which is information about the decoded result, to the input terminal of the first component decoder 101 through the deinterleaver 109.
    The configuration decoder selects a path having a small error by performing metric calculation and comparison in each state with a branch metric calculation unit (BMC) 113 that calculates a branch metric as shown in FIG. An addition comparison selecting section (Add & Compare & Selection: ACS) 115 is provided.
    In general, in the case of a decoder that performs repeated decoding as described above, a metric value (Mt) is calculated by Equation 1 below.
    M t : Calculated metric for t time
    u t : Codeword for signword bit
    X t, j : Codeword for Redundancy
    y t, j : Value received from the channel
    Lc: channel confidence value
    L (ut) : Leading confidence value for t time
    As shown in Equation 1, the state value Mt is accumulated by the second, third, and fourth terms. Basically, when implementing in hardware, these values should be within a certain range so that they can be implemented without overflow problem. However, iterative decoder basically needs to iteratively decode in order to improve the decoding performance (BER / FER), so that the value of each state continues to increase so that the state value for each state is out of a certain range considered in the hardware implementation. This makes hardware implementation impossible.
    Accordingly, an object of the present invention is a state value normalization device of a mobile communication system component decoder for outputting the normalized to a predetermined level by subtracting a predetermined value when all the accumulated state values of each current state in the mobile communication system decoder In providing a method.
    In order to achieve the above another object, the present invention provides a configuration decoder of a mobile communication system repeater in which at least two or more component decoders are connected in a serial chain structure and decoded by a repetitive decoding method, each transitioning from a current state to a next state. A state value of a state is detected, and when the state value of each state exceeds a predetermined reference value, the state value is subtracted to a predetermined value and normalized, and then the state value is transitioned to the next state.
    In order to achieve the above object, the present invention provides a method for normalizing a state value of a mobile communication system component decoder in which at least two or more component decoders are connected in a serial chain structure and decoded by an iterative decoding method. Detecting a state value; checking whether all accumulated state values of the detected current state exceed a preset reference value; and if all accumulated state values exceed a preset reference value, a predetermined value from each accumulated state value. After subtracting the normalized cumulative state value, and then performs a normal operation.
    1 is a block diagram of a repeating decoder having two component decoders to which the present invention is applied.
    2 is a block diagram of a configuration decoder to which the present invention is applied;
    3 is a block diagram of an addition comparison selecting unit having a state value normalizing device according to a first embodiment of the present invention;
    4 is a flowchart illustrating a state value normalization method according to a first embodiment of the present invention;
    5 is a block diagram of an addition comparison selecting unit having a state value normalization device according to a second embodiment of the present invention;
    FIG. 6 illustrates a format of a state value storage memory for normalizing state values according to FIG.
    7 is a flowchart illustrating a state value normalization method according to a second embodiment of the present invention;
    8A and 8B are diagrams for explaining a correct path, an error path, and a path difference.
    9A, 9B and 9C show the correct path and the error path according to the signal to noise ratio.
    10 is a diagram for explaining that the Δ max value is saturated according to an energy-to-noise power ratio.
    Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. First, in adding reference numerals to the components of each drawing, it should be noted that the same reference numerals have the same reference numerals as much as possible even if displayed on different drawings. In the following description of the present invention, if it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.
    The add comparison selector 115 of the constituent decoder according to the present invention performs a function of subtracting and normalizing each state value to a predetermined value when the state values exceed the reference value.
    According to an embodiment of the present invention, there are two methods for standardizing a cumulative state value. The first method is to normalize the cumulative state value by using the smallest cumulative state value among the cumulative state values when the cumulative state values of the respective states exceed a predetermined reference value. When the reference value is exceeded, the cumulative state value is normalized using a constant value.
    First, the first method will be described with reference to FIG. 3. FIG. 3 is a block diagram of an addition comparison selector having a state value normalizing device when the restriction length K is 3 according to the first embodiment of the present invention. Drawing. The configuration and operation of the state value normalizing device according to the present invention will be described with reference to FIG.
    If constraint K = 3, the number of memories is two and the number of states is four. The comparator 117 has a predetermined reference value, and detects the state values of the respective current states, respectively. If each detected state value exceeds the reference value, the comparator outputs a predetermined value to the subtractor 125 connected between the current state and the next state, respectively. Then, each subtractor 125 subtracts a predetermined value from the accumulated state value of the current state, and outputs the next state.
    4 is a diagram illustrating a cumulative state value normalization method according to the first method.
    Referring to FIG. 4, first, the comparator 117 detects state values for four current states in step 401. When each of the state values is detected, the comparator 117 checks whether each state value exceeds a preset reference value in step 403. If any one of the state values does not exceed the reference value in step 403, the comparator 1170 proceeds to step 405 to perform normal addition, comparison, and selection operations. However, if each of the detected accumulated state values exceeds the reference value, the comparator 117 proceeds to step 405 and outputs the smallest accumulated state value among the accumulated state values to each of the subtractors 125. Then, each subtractor 125 receives the smallest accumulated state value, subtracts the smallest accumulated state value from each accumulated state value, and transitions to the next state, and performs normal operation of addition, comparison, and selection in step 407. .
    The second method will now be described with reference to FIGS. 5, 6 and 7.
    5 shows the configuration of a comparator 117 according to a second method of the present invention. Hereinafter, referring to FIG. 5, the comparator 117 may include a plurality of memories 123, 125, 127, and 129 and respective memories 123, 125, 127, and 129 that store cumulative state values of respective states. An AND gate 121 for determining whether all stored state values exceed a reference value, and a high signal is inputted from the AND gate to determine the most significant bit value of each of the plurality of memories 123, 125, 127, and 129. And an inverting portion 119 for resetting.
    Before explaining the operation of the comparator 117, the configuration of the memory will be described with reference to FIG.
    Here, the accumulated state value is assumed to be 8 bits per sample, and it is assumed that 1 bit is added to prevent the accumulated state value from overflowing. Therefore, the cumulative state value has 9 bits per sample in total. The AND gate 121 receives the most significant bit (MSB) value of the memories 123, 125, 127, and 129. The AND gate 121 generates a signal only when all inputs are 1. Accordingly, no signal is generated unless the most significant bit of the plurality of memories 123, 125, 127, and 129 has a value of "1". Therefore, when the state values of each memory are accumulated and the value of the most significant bit becomes "1", the AND gate 121 generates and outputs a signal (high). At this time, the inverting unit 119 receives the signal from the AND gate 121 and outputs a reset signal to the most significant bit to reset. This is equivalent to subtracting 256 from the cumulative state value when the cumulative state value is represented by 8 bits.
    And the difference between the cumulative state values Δ k m = (u k i -u k j ) ≤Δ max Assume that i, j, k is one of 0, 1, 2, and 3. Assume that Δ max = 255 = 2 8 -1. Finally, it is assumed that u k 1 is a cumulative state value having a minimum value and u k 3 is a cumulative state value of a maximum value.
    If the MSB 1 bit of u k 3 is "1" in the above assumption, the MSB 1 bit of the remaining states becomes "0" or "1". However, u k 3 does not cause another carry out before all MSBs of U k i , 0 ≦ i ≦ 3 become “1. That is, until all MSBs become“ 1 ” u k i never causes a carry out on the 9th bit, if all MSBs of all states are "1", then subtract 256 from each state value, because if the MSB of all state values is "1", The minimum value of the values is 256, so subtracting 256 does not underflow.
    7 is a flowchart illustrating a state value normalization method according to the second method.
    Hereinafter, referring to FIG. 7, the AND gate 121 of the comparator 117 detects, that is, receives MSB values of cumulative state values of respective current states in step 501. When the values of the MSBs of the respective current states are input, the AND gate 121 determines whether the value of each MSB is 1. If any one of the values of the cumulative MSB is not "1", the process proceeds to step 507 to perform a normal operation. Outputs Then, in step 505, the inverting unit 119 receives the signal and outputs a reset signal to the MSBs of the respective accumulated state values to reset the values of the MSBs. When the value of the MSB is reset, normal operation of addition, comparison, and selection is performed until the values of the MSB are all "1" in step 507.
    The above-mentioned Δ max will be described in detail with reference to FIGS. 8 to 10.
    Δ max has a small value at Low Eb / No, and has a large value at High Eb / No. Therefore, the problem is how much Δ max is set at high Eb / No. Of course, the simple idea is that when Eb / No → infinity, Δ max can be thought of as infinite, but as in SOVA, the metric difference is saturated by D free .
    For example, assuming 4 (bits / sample) and transmitting an all zero codeword ('000') in a convolutional code with code rate R = 1/3 (K = 9), as shown in FIG. As shown, in the case of high Eb / No, most of the errors are errors occurring in the comparison / selection of the all zero path and the d free path. Here, the branch metric value is calculated by Equation 2, and the path metric value is calculated by Equation 3.

    I = 0, 1, 2, 3
    This is Δ k i = u s, k i -u c, k i where 's' is the Survivor Path and 'c' is the Competition Path. In any state (i), there is a difference between the two path metrics. Here, since the paths are all zero paths and d free paths, the difference between the two paths is as much as d free code symbols.
    Therefore, the metric difference in the above case is as follows.
    (K = 9, R = 1/3, d free of CC = 18)
    Δ N = | u s, N o -u c, N o |
    = | M- (M + d free × 15) |
    = | d free × 15 | = 18 × 15 = 270
    to be. Δ max ≤ 270. Therefore, it can be seen that it is shown in Figure 9 according to the signal-to-noise ratio (S / N).
    Fig. 9A shows Δ max at a high level signal-to-noise ratio, and the Δ max value is calculated by Equation 4 below.
    (Equation 4)
    Δ max = d free × Max (Q [ctot])
    Q means quantization level and Max (Q [.]) Means the distance between '0' and '1'. For example, if Q = 16, Max (Q [.]) = 15, and if Q = 8, Max {(Q [.]) = 7.
    9B is a diagram illustrating Δ max in a signal-to-noise ratio of a medium level, wherein Δ max is calculated by Equation 5 below.
    (Equation 5)
    Δ max = (d free + δ) × Max (Q [ctot])
    Δ is a very small value. This value is less than or equal to 2 x d free x Max (Q [.]) In CC.
    FIG. 9C shows Δ max at a low level signal-to-noise ratio, wherein Δ max is calculated by Equation 6 below.
    (Equation 6)
    Δ max = (d free -δ) × Max (Q [ctot])
    Therefore, we consider that Δ max increases little by little as Eb / No increases, and from that point, the value saturates as shown in FIG. 10.
    Hereinafter, the characteristics of C.C in CDMA 200 will be described by way of example.
    When K = 9, when R = 1/2, d free = 12, next⇒14, 16, 18, 20, ...
    When R = 1/3, d free = 18, then ⇒20, 22, ...
    When R = 1/4, d free = 24, next⇒26, 18, ...
    to be. Δ max in the CC is shown in Table 1 below.
    C.C characteristicsΔ max (d free = 12)Next d freek = 9, R = 1/215 × 12 = 180210 (15 × 14) to 240 (15 × 16) R = 1/315 × 18 = 270300 (15 × 20) to 330 (15 × 22) R = 1/415 × 24 × 360390 (15 × 26) to 420 (15 × 28)
    Accordingly, the number of bits to be attached in order to prevent the overflow of 8 bits / sample allocated to the above state value is as follows.
    1 bit at R = 1/2 (2 8 = 256, 240 <256), 2 bits at R = 1/3 (2 9 = 512, 330 <512) and 2 bits at R = 1/4 (2 9 = 512, 420 &lt; 512). Therefore, it is possible to have as much as 2 bits to prevent overflow.
    As described above, the present invention can eliminate errors due to overflow by normalizing an accumulated state value performed for decoding, and there is an advantage in that the memory can be efficiently used.
    权利要求:
    Claims (9)
    [1" claim-type="Currently amended] In the configuration decoder of the mobile communication system repeater which at least two or more component decoders are connected in a serial chain structure and decoded by the iterative decoding method,
    Detects the state value of each state that transitions from the current state to the next state, if the state value of each state exceeds a predetermined reference value, subtracts and normalizes the state value to a predetermined value, and then transitions the state value to the next state. A device for normalizing the state value of a component decoder, characterized in that.
    [2" claim-type="Currently amended] 2. The normalization apparatus according to claim 1, wherein the normalizing of the state value is an add comparison selector.
    [3" claim-type="Currently amended] The method of claim 1, wherein the addition comparison selection unit,
    A plurality of current states are respectively connected between the next states corresponding to each of the current states, and the normalized state values are output to the next state by receiving and adding a state value input from the current state and a predetermined negative value, respectively. The same number of adders as the number of states described above,
    And a comparator for detecting each cumulative state value of the current state and outputting a predetermined negative value to each adder if all of the state values of the current state exceed a reference value.
    [4" claim-type="Currently amended] 4. The apparatus of claim 3, wherein the predetermined negative value is the smallest accumulated state value of each of the accumulated state values.
    [5" claim-type="Currently amended] 4. The apparatus of claim 3, wherein the predetermined negative value is a predetermined random value.
    [6" claim-type="Currently amended] The method of claim 3, wherein the addition comparison selection unit,
    An AND gate receiving and ORing the most significant bit of each of the plurality of current states;
    When the signal output from the AND gate is high, it is characterized in that it comprises an inverting unit for applying a reset signal to the most significant bit of each of the current state to reset.
    [7" claim-type="Currently amended] In the method of normalizing the state value of a mobile communication system component decoder in which at least two component decoders are connected in a serial chain structure and decoded by an iterative decoding method,
    Detecting a cumulative state value of each of the plurality of current states;
    Checking whether all accumulated state values of the detected current state exceed a preset reference value;
    And if the cumulative state values exceed a preset reference value, normalizing the cumulative state values by subtracting a predetermined value from each cumulative state value, and then performing a normal operation.
    [8" claim-type="Currently amended] 6. The method of claim 5, wherein the predetermined value is the smallest value among the cumulative state values of the current state.
    [9" claim-type="Currently amended] The method of claim 5, wherein the predetermined value is a predetermined random value.
    类似技术:
    公开号 | 公开日 | 专利标题
    US7310768B2|2007-12-18|Iterative decoder employing multiple external code error checks to lower the error floor
    AU682542B2|1997-10-09|Multirate serial viterbi decoder for code division multiple access system applications
    US7191377B2|2007-03-13|Combined turbo-code/convolutional code decoder, in particular for mobile radio systems
    US5295142A|1994-03-15|Viterbi decoder
    KR100803957B1|2008-02-15|Highly parallel map decoder
    US6982659B2|2006-01-03|Method and apparatus for iterative decoding
    RU2216851C2|2003-11-20|Iterative decoder and iterative decoding method for communication system
    JP5133760B2|2013-01-30|Random access multi-direction CDMA2000 turbo code interleaver
    EP1162750B1|2004-03-10|MAP decoder with correction function in LOG-MAX approximation
    EP1706953B1|2007-09-26|Method and system for calculating the bit error rate of a received signal
    US7467347B2|2008-12-16|Method for decoding error correcting code, its program and its device
    US7643558B2|2010-01-05|Method, apparatus, and system for encoding and decoding side information for multimedia transmission
    KR100634071B1|2006-10-13|Method and apparatus for performing decoding of crc outer concatenated codes
    KR100549894B1|2006-02-06|Encoding device, encoding method, mobile station and base station
    US6292918B1|2001-09-18|Efficient iterative decoding
    JP4805883B2|2011-11-02|Space efficient turbo decoder
    JP3677257B2|2005-07-27|Convolution decoding device
    US6891484B2|2005-05-10|Method of decoding a variable-length codeword sequence
    JP3822249B2|2006-09-13|Method and means for detecting communication signals with non-uniform error protection
    US7577899B2|2009-08-18|Cyclic redundancy check | based error correction method and device
    KR101297060B1|2013-08-19|Multidimensional block encoder with sub-block interleaver and de-interleaver
    US7607073B1|2009-10-20|Methods, algorithms, software, circuits, receivers and systems for iteratively decoding a tailbiting convolutional code
    US7107509B2|2006-09-12|Higher radix Log MAP processor
    JP4777876B2|2011-09-21|Early termination of turbo decoder iterations
    US7539256B2|2009-05-26|Decoding device and decoding method
    同族专利:
    公开号 | 公开日
    BR9916685A|2001-09-25|
    EP1145458A1|2001-10-17|
    CA2354466A1|2000-07-13|
    JP2003523105A|2003-07-29|
    CN1376337A|2002-10-23|
    WO2000041328A1|2000-07-13|
    RU2214680C2|2003-10-20|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    1998-12-31|Application filed by 윤종용, 삼성전자 주식회사
    1998-12-31|Priority to KR1019980062724A
    1998-12-31|Priority claimed from KR1019980062724A
    2000-07-25|Publication of KR20000046049A
    2001-01-15|Application granted
    2001-01-15|Publication of KR100276814B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR1019980062724A|KR100276814B1|1998-12-31|Apparatus and Method for Normalizing State Value of Component Decoder in Mobile Communication System|
    [返回顶部]